1. Field of the Invention
The present invention relates to a heat treatment method for reducing in a simple and reliable manner micro-defects which exist in the surface of a single-crystal wafer of semiconductor silicon. The present invention also relates to a silicon wafer which is heat-treated by the above method.
2. Description of the Related Art
Along with a recent tendency to increase the degree of integration and precision of semiconductor integrated circuits, there has been an increasing demand for semiconductor silicon wafers having larger diameters and higher quality. Such silicon wafers are manufactured in a manner in which a cylindrical single-crystal silicon ingot is sliced into wafers, and the surfaces of the sliced wafers are then mirror-polished. A single-crystal silicon ingot is usually manufactured by the Czochralski method (pulling method).
CZ silicon wafers manufactured from a single-crystal silicon ingot grown by the Czochralski method contain micro-defects which are generated due to precipitation of oxygen or the like and which serve as nuclei of oxidation induced stacking faults and crystal defects (grown-in defects) called COP (crystal originated particles). The presence of these defects is a cause of a deterioration in electric characteristics of semiconductor devices; for example, an increase in leak current and a reduction in oxide dielectric breakdown voltage.
Accordingly, in order to prevent the aforementioned crystal defects from generating in a grown crystal in the stage of growing a single-crystal silicon ingot by the Czochralski method, various efforts are made to increase purity of material or members used and to determine appropriate conditions of crystal growth. For example, growing crystal at a low pulling rate is reported to be effective for reducing COP. However, at such a low growth rate, nuclei of oxidation induced stacking faults cannot be reduced in number. Particularly, when a crystal having as large a diameter as 300 mm or more is grown at such a low growth rate, nuclei of oxidation induced stacking faults are reported to even increase in number and occur densely in a ring-shaped area.
Thus, there have been developed methods of suppressing the generation of oxidation induced stacking faults in silicon wafers by heat treatment even when micro-defects, which serve as nuclei of oxidation induced stacking faults, are generated in a single-crystal silicon ingot in its growing stage, and silicon wafers manufactured from the single-crystal silicon ingot also contain crystal defects.
One of these methods is disclosed in Japanese Patent Application Laid-Open (kokai) No. 7-165495. According to heat treatment described in the publication, silicon wafers are subjected to heat treatment in a hydrogen gas atmosphere at a temperature ranging from 1000.degree. C. to 1350.degree. C. for at least 30 minutes to thereby reduce the density of oxidation induced stacking faults.
This method is effective to a certain degree for the reduction of oxidation induced stacking faults in the surface of a wafer. However, the method is dangerous due to the use of hydrogen gas as a heat treatment ambient gas. Further, a heat treatment apparatus must employ a special explosion-proof feature, which makes the apparatus complex and expensive and involves complicated operations. Also, the heat treatment time is relatively long. From the viewpoint of the process time extending from loading of wafers into a heat treatment furnace to unloading therefrom, the method is poor in productivity and high in cost. Additionally, the surfaces of the thus-heat-treated wafer still contain approximately 50 oxidation induced stacking faults per square centimeter.
A heat treatment method which does not use hydrogen is proposed in Japanese Patent Application Laid-Open (kokai) No. 7-45622. According to this method, until wafers reach a temperature of 1100.degree. C. to 1200.degree. C., in a non-oxidation atmosphere the wafers are heated at such a temperature-rising rate as not to cause slip dislocation in the wafers, and then cooled at such a temperature-lowering rate as not to cause slip dislocation in the wafers.
This method is also effective to a certain degree for the reduction of oxidation induced stacking faults, but requires a relatively long time for heat treatment. Particularly, such a temperature-rising or -lowering rate as not to cause slip dislocation in a wafer means, for example, 20.degree. C./min to 30.degree. C./min, indicating that time required for loading wafers into or unloading from a heat treatment furnace is relatively long. Thus, the overall process time covering loading, heat treatment, and unloading is relatively long, so that this method is also poor in productivity and high in cost.
As described above, conventionally, silicon wafers have been heat-treated in batches. In order to prevent slip dislocation from generating in peripheral portions of wafers, wafers at room temperature are gradually loaded at a speed of 15 cm/min into a heat treatment furnace maintained at a temperature lower than 1000.degree. C. Upon completion of loading, the heat treatment furnace is heated to a desired temperature at a slow rate of, for example, 10.degree. C./min. After the wafers are heat-treated at the desired temperature, the heat treatment furnace is cooled to a temperature lower than 1000.degree. C. at a slow rate of, for example, 5.degree. C./min. Thereafter, the heat-treated wafers are unloaded from the heat treatment furnace at a slow speed; for example, a speed identical to the loading speed.
Accordingly, as mentioned previously, each step of the heat treatment process, specifically loading of wafers into a heat treatment furnace, temperature raising, heat treatment, temperature lowering, and unloading, requires a relatively long time. As a result, the overall productivity of the heat treatment process is reduced, and the heat treatment cost increases significantly.